Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1986, volume: 5, number: 4

1. Stephen D. Posluszny
   SLS: An Advanced Symbolic Layout System for Bipolar and FET Design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:450-458 [Journal]
   
2. Howard H. Chen, Ernest S. Kuh
   Glitter: A Gridless Variable-Width Channel Router. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:459-465 [Journal]
   
3. Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki
   A Hardware Maze Router with Application to Interactive Rip-Up and Reroute. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:466-476 [Journal]
   
4. David P. La Potin, Stephen W. Director
   Mason: A Global Floorplanning Approach for VLSI Design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:477-489 [Journal]
   
5. Martin L. Resnick
   SPARTA: A System Partitioning Aid. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:490-498 [Journal]
   
6. Claudio Turchetti, P. Prioretti, Guido Masetti, E. Profumo, Massimo Vanzi
   A Meyer-Like Approach for the Transient Analysis of Digital MOS IC's. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:499-507 [Journal]
   
7. Rahul Razdan, Andrzej J. Strojwas
   A Statistical Design Rule Developer. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:508-520 [Journal]
   
8. Kenneth S. Kundert, Alberto L. Sangiovanni-Vincentelli
   Simulation of Nonlinear Circuits in the Frequency Domain. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:521-535 [Journal]
   
9. David Tsao, Chin-Fu Chen
   A Fast-Timing Simulator for Digital MOS Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:536-540 [Journal]
   
10. D. M. H. Walker, Stephen W. Director
    VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:541-556 [Journal]
    
11. Hsi-Ching Shih, Joseph T. Rahmeh, Jacob A. Abraham
    FAUST: An MOS Fault Simulator with Timing Information. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:557-563 [Journal]
    
12. Ki Soo Hwang, M. Ray Mercer
    Derivation and Refinement of Fan-Out Constraints to Generate Tests in Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:564-572 [Journal]
    
13. Hasan Elhuni, Anastasios Vergis, Larry L. Kinney
    C-Testability of Two-Dimensional Iterative Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:573-581 [Journal]
    
14. Karen A. Bartlett, William W. Cohen, Aart J. de Geus, Gary D. Hachtel
    Synthesis and Optimization of Multilevel Logic under Timing Constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:582-596 [Journal]
    
15. Giovanni De Micheli
    Symbolic Design of Combinational and Sequential Logic Circuits Implemented by Two-Level Logic Macros. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:597-616 [Journal]
    
16. Prathima Agrawal
    Concurrency and Communication in Hardware Simulators. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:617-623 [Journal]
    
17. T. Shima
    Table Lookup MOSFET Capacitance Model for Short-Channel Devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:624-632 [Journal]
    
18. Ruey-Sing Wei, Alberto L. Sangiovanni-Vincentelli
    PLATYPUS: A PLA Test Pattern Generation Tool. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:633-644 [Journal]
    
19. Jeffrey Y.-F. Tang, S. E. Laux
    MONTE: A Program to Simulate the Heterojunction Devices in Two Dimensions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:645-652 [Journal]
    
20. Surya Veeraraghavan, Jerry G. Fossum, William R. Eisenstadt
    SPICE Simulation of SOI MOSFET Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:653-658 [Journal]
    
21. Mark Douglas Matson, Lance A. Glasser
    Macromodeling and Optimization of Digital MOS VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:659-678 [Journal]
    
22. Martin D. Giles
    Ion Implantation Calculations in Two Dimensions Using the Boltzmann Transport Equation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:679-684 [Journal]