Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1995, volume: 14, number: 9

1. Bernd Becker, Rolf Drechsler, Paul Molitor
   On the generation of area-time optimal testable adders. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1049-1066 [Journal]
   
2. Pranav Ashar, Sujit Dey, Sharad Malik
   Exploiting multicycle false paths in the performance optimization of sequential logic circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1067-1075 [Journal]
   
3. Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
   Combining technology mapping and placement for delay-minimization in FPGA designs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1076-1084 [Journal]
   
4. Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof
   Local ratio cut and set covering partitioning for huge logic emulation systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1085-1092 [Journal]
   
5. Akira Ito
   A voltage dependent capacitance model including effects of manufacturing process variabilities on voltage coefficients. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1093-1097 [Journal]
   
6. Ming-Huei Shieh, Hung Chang Lin
   Modeling hysteretic current-voltage characteristics for resonant tunneling diodes. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1098-1103 [Journal]
   
7. Ernst Strasser, Siegfried Selberherr
   Algorithms and models for cellular based topography simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1104-1114 [Journal]
   
8. Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal
   Test function embedding algorithms with application to interconnected finite state machines. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1115-1127 [Journal]
   
9. Soo Young Lee, Kewal K. Saluja
   Test application time reduction for sequential circuits with scan. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1128-1140 [Journal]
   
10. Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy
    Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1141-1154 [Journal]
    
11. Vishwani D. Agrawal, Srimat T. Chakradhar
    Combinational ATPG theorems for identifying untestable faults in sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1155-1160 [Journal]
    
12. Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia
    Pseudo-exhaustive built-in TPG for sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1160-1171 [Journal]
    
13. Vijay Raghavendra, Chidchanok Lursinsap
    A technique for micro-rollback self-recovery synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1171-1179 [Journal]