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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1992, volume: 11, number: 5

  1. TingTing Hwang, Robert Michael Owens, Mary Jane Irwin
    Efficiently computing communication complexity for multilevel logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:545-554 [Journal]
  2. David M. Lewis
    A compiled-code hardware accelerator for circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:555-565 [Journal]
  3. Luis Miguel Silveira, Jacob K. White, Horácio C. Neto, Luís M. Vidigal
    On exponential fitting for circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:566-574 [Journal]
  4. Rakesh Chadha, Chandramouli Visweswariah, Chin-Fu Chen
    M3-a multilevel mixed-mode mixed A/D simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:575-585 [Journal]
  5. John Y. Lee, Xiaoli Huang, Ronald A. Rohrer
    Pole and zero sensitivity calculation in asymptotic waveform evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:586-597 [Journal]
  6. Donald J. Erdman, Donald J. Rose
    Newton waveform relaxation techniques for tightly coupled systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:598-606 [Journal]
  7. John F. Beetem
    Hierarchical topological sorting of apparent loops via partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:607-619 [Journal]
  8. Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic
    A detailed router for field-programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:620-628 [Journal]
  9. John R. F. McMacken, Savvas G. Chamberlain
    A numerical model for two-dimensional transient simulation of amorphous silicon thin-film transistors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:629-637 [Journal]
  10. José Pineda de Gyvez, Chennian Di
    IC defect sensitivity for footprint-type spot defects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:638-658 [Journal]
  11. Kuen-Jong Lee, Melvin A. Breuer
    Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:659-670 [Journal]
  12. Deodatta R. Apte, Mark E. Law
    Comparison of iterative methods for AC analysis in PISCES-IIB. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:671-673 [Journal]
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