Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1997, volume: 16, number: 7

1. Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
   Implicit computation of compatible sets for state minimization of ISFSMs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:657-676 [Journal]
   
2. Tiziano Villa, Timothy Kam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
   Explicit and implicit algorithms for binate covering problems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:677-691 [Journal]
   
3. Tiziano Villa, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
   Symbolic two-level minimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:692-708 [Journal]
   
4. Lars W. Hagen, Andrew B. Kahng
   Combining problem reduction and adaptive multistart: a new technique for superior iterative partitioning. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:709-717 [Journal]
   
5. Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
   Analytical estimation of signal transition activity from word-level statistics. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:718-733 [Journal]
   
6. Kevin J. Kerns, Andrew T. Yang
   Stable and efficient reduction of large, multiport RC networks by pole analysis via congruence transformations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:734-744 [Journal]
   
7. Karim Arabi, Bozena Kaminska
   Testing analog and mixed-signal integrated circuits using oscillation-test method. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:745-753 [Journal]
   
8. Manjit Borah, Robert Michael Owens, Mary Jane Irwin
   A fast algorithm for minimizing the Elmore delay to identified critical sinks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:753-759 [Journal]
   
9. Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel
   Improving a nonenumerative method to estimate path delay fault coverage. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:759-762 [Journal]
   
10. Peter M. Maurer
    The inversion algorithm for digital simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:762-769 [Journal]
    
11. Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
    On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:770-776 [Journal]
    
12. Hsiao-Pin Su, Youn-Long Lin
    A phase assignment method for virtual-wire-based hardware emulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:776-783 [Journal]
    
13. Nur A. Touba, Edward J. McCluskey
    Logic synthesis of multilevel circuits with concurrent error detection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:783-789 [Journal]