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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1990, volume: 9, number: 7

  1. Forrest Brewer, Daniel D. Gajski
    Chippe: a system for constraint driven behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:7, pp:681-695 [Journal]
  2. Prathima Agrawal, Scott H. Robinson, Thomas G. Szymanski
    Automatic modeling of switch-level networks using partial orders [MOS circuits]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:7, pp:696-707 [Journal]
  3. Robert L. Maziasz, John P. Hayes
    Layout optimization of static CMOS functional cells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:7, pp:708-719 [Journal]
  4. W. T. Liou, Jimmy J. M. Tan, Richard C. T. Lee
    Minimum rectangular partition problem for simple rectilinear polygons. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:7, pp:720-733 [Journal]
  5. Michael D. Osterman, Michael G. Pecht
    Placement for reliability and routability of convectively cooled PWBs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:7, pp:734-744 [Journal]
  6. Shintaro Ushio, Kenji Nishi, Shigeki Kuroda, Kazuhiko Kai, Jun Ueda
    A fast three-dimensional process simulator OPUS/3D with access to two-dimensional simulation results. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:7, pp:745-751 [Journal]
  7. Debashis Bhattacharya, John P. Hayes
    Designing for high-level test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:7, pp:752-766 [Journal]
  8. Micaela Serra, Terry Slater, Jon C. Muzio, D. Michael Miller
    The analysis of one-dimensional linear cellular automata and their aliasing properties. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:7, pp:767-778 [Journal]
  9. Doron Drusinsky-Yoresh
    Symbolic cover minimization of fully I/O specified finite state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:7, pp:779-781 [Journal]
  10. Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu
    A fast transistor-chaining algorithm for CMOS cell layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:7, pp:781-786 [Journal]
  11. Nripendra N. Biswas
    On covering distant minterms by the camp algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:7, pp:786-789 [Journal]
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