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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1989, volume: 8, number: 1

  1. S. S.-S. Chung
    A charge-based capacitance model of short-channel MOSFETs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:1, pp:1-7 [Journal]
  2. Young hwan Kim, Seung Ho Hwang, A. Richard Newton
    Electrical-logic simulation and its applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:1, pp:8-22 [Journal]
  3. Kenji Nishi, Kouichi Sakamoto, Shigeki Kuroda, Jun Ueda, Tatsurou Miyoshi, Shintaro Ushio
    A general-purpose two-dimensional process simulator-OPUS for arbitrary structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:1, pp:23-32 [Journal]
  4. Pramod V. Argade
    Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:1, pp:33-40 [Journal]
  5. John Horan, Colin Lyden, Alan Mathewson, Ciaran G. Cahill, W. A. Lane
    Analysis of distributed resistance effects in MOS transistors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:1, pp:41-45 [Journal]
  6. Andrzej Krasniewski, Slawomir Pilarski
    Circular self-test path: a low-cost BIST technique for VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:1, pp:46-55 [Journal]
  7. Wing Ning Li, Sudhakar M. Reddy, Sartaj K. Sahni
    On path selection in combinational logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:1, pp:56-63 [Journal]
  8. Gary D. Hachtel, Christopher R. Morrison
    Linear complexity algorithms for hierarchical routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:1, pp:64-80 [Journal]
  9. Fadi J. Kurdahi, Alice C. Parker
    Techniques for area estimation of VLSI layouts. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:1, pp:81-92 [Journal]
  10. Susheel J. Chandra, Janak H. Patel
    Experimental evaluation of testability measures for test generation (logic circuits). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:1, pp:93-97 [Journal]
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