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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1993, volume: 12, number: 2

  1. Hsi-Chuan Chen, David Hung-Chang Du, Li-Ren Liu
    Critical path selection for performance optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:185-195 [Journal]
  2. Hsi-Chuan Chen, David Hung-Chang Du
    Path sensitization in critical path problem [logic circuit design]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:196-207 [Journal]
  3. Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli
    Automatic generation of parasitic constraints for performance-constrained physical design of analog circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:208-224 [Journal]
  4. Richard Burch, Ping Yang, Paul F. Cox, Kartikeya Mayaram
    A new matrix solution technique for general circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:225-241 [Journal]
  5. Ren-Song Tsay
    An exact zero-skew clock routing algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:242-249 [Journal]
  6. Bin Zhu, Xinya Wu, Wenjun Zhuang, Wai-Kai Chen
    A new one-and-half layer channel routing algorithm based on assigning resources for CMOS gate array. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:250-264 [Journal]
  7. Nils Hedenstierna, Kjell O. Jeppson
    The halo algorithm-an algorithm for hierarchical design of rule checking of VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:265-272 [Journal]
  8. Keumog Ahn, Sartaj Sahni
    Constrained via minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:273-282 [Journal]
  9. D. M. H. Walker, Chris S. Kellen, David M. Svoboda, Andrzej J. Strojwas
    The CDB/HCDB semiconductor wafer representation server. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:283-295 [Journal]
  10. ShaoWei Pan, Yu Hen Hu
    PYFS-a statistical optimization method for integrated circuit yield enhancement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:296-309 [Journal]
  11. Farid N. Najm
    Transition density: a new measure of activity in digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:310-323 [Journal]
  12. Ahmadreza Rofougaran, Asad A. Abidi
    A table lookup FET model for accurate analog circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:324-335 [Journal]
  13. Wen-Ben Jone
    Defect level estimation of circuit testing using sequential statistical analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:336-348 [Journal]
  14. Dwight D. Hill, Nam Sung Woo
    The benefits of flexibility in lookup table-based FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:349-353 [Journal]
  15. Wolfgang Rülling, Thomas Schilz
    A new method for hierarchical compaction [VLSI]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:353-360 [Journal]
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