Ren-Song Tsay An exact zero-skew clock routing algorithm. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:242-249 [Journal]

Bin Zhu, Xinya Wu, Wenjun Zhuang, Wai-Kai Chen A new one-and-half layer channel routing algorithm based on assigning resources for CMOS gate array. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:250-264 [Journal]

Nils Hedenstierna, Kjell O. Jeppson The halo algorithm-an algorithm for hierarchical design of rule checking of VLSI circuits. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:265-272 [Journal]

ShaoWei Pan, Yu Hen Hu PYFS-a statistical optimization method for integrated circuit yield enhancement. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:296-309 [Journal]

Farid N. Najm Transition density: a new measure of activity in digital circuits. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:310-323 [Journal]

Wen-Ben Jone Defect level estimation of circuit testing using sequential statistical analysis. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:336-348 [Journal]

Dwight D. Hill, Nam Sung Woo The benefits of flexibility in lookup table-based FPGAs. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:349-353 [Journal]