Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1996, volume: 15, number: 1

1. Michiko Miura-Mattausch, Ute Feldmann, Alexander Rahm, Michael Bollu, Dominique Savignac
   Unified complete MOSFET model for analysis of digital and analog circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:1-7 [Journal]
   
2. Andrew B. Kahng, Chung-Wen Albert Tsao
   Planar-DME: a single-layer zero-skew clock tree router. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:8-19 [Journal]
   
3. Wolfgang Kunz, Dhiraj K. Pradhan, Sudhakar M. Reddy
   A novel framework for logic verification in a synthesis environment. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:20-32 [Journal]
   
4. Yu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska
   Graph based analysis of 2-D FPGA routing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:33-44 [Journal]
   
5. Ivan P. Radivojevic, Forrest Brewer
   A new symbolic technique for control-dependent scheduling. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:45-57 [Journal]
   
6. Narain D. Arora, Kartik V. Raol, Reinhard Schumann, Llanda M. Richardson
   Modeling and extraction of interconnect capacitances for multilayer VLSI circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:58-67 [Journal]
   
7. Resve A. Saleh, Brian A. A. Antao, Jaidip Singh
   Multilevel and mixed-domain simulation of analog circuits and systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:68-82 [Journal]
   
8. Chingwei Yeh, Chi-Shong Wang
   On the integration of partitioning and global routing for rectilinear placement problems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:83-91 [Journal]
   
9. Nikos Glezos, Ioannis Raptis
   A fast electron beam lithography simulator based on the Boltzmann transport equation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:92-102 [Journal]
   
10. Si-Qing Zheng, Joon Shink Lim, S. Sitharama Iyengar
    Finding obstacle-avoiding shortest paths using implicit connection graphs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:103-110 [Journal]
    
11. Glenn Jennings, Esther Jennings
    A discrete syntax for level-sensitive latched circuits having n clocks and m phases. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:111-126 [Journal]
    
12. Jochen Bern, Christoph Meinel, Anna Slobodová
    Some heuristics for generating tree-like FBDD types. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:127-130 [Journal]
    
13. Jochen Bern, Christoph Meinel, Anna Slobodová
    Global rebuilding of OBDD's avoiding memory requirement maxima. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:131-134 [Journal]