Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2006, volume: 25, number: 8

1. Hua Tang, Hui Zhang, Alex Doboli
   Refinement-based synthesis of continuous-time analog filters through successive domain pruning, plateau search, and adaptive sampling. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1421-1440 [Journal]
   
2. Behzad Akbarpour, Sofiène Tahar
   An approach for the formal verification of DSP designs using Theorem proving. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1441-1457 [Journal]
   
3. Hiren D. Patel, Deepak Mathaikutty, David Berner, Sandeep K. Shukla
   CARH: service-oriented architecture for validating system-level designs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1458-1474 [Journal]
   
4. Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester
   Gate-length biasing for runtime-leakage control. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1475-1485 [Journal]
   
5. Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
   Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1486-1495 [Journal]
   
6. Zhenyu Qi, Hao Yu, Pu Liu, Sheldon X.-D. Tan, Lei He
   Wideband passive multiport model order reduction and realization of RLCM circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1496-1509 [Journal]
   
7. Muhammet Mustafa Ozdal, Martin D. F. Wong
   Algorithms for simultaneous escape routing and Layer assignment of dense PCBs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1510-1522 [Journal]
   
8. P. Kannan, D. Bhatia
   Interconnect estimation for FPGAs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1523-1534 [Journal]
   
9. Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng
   Pseudofunctional testing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1535-1546 [Journal]
   
10. Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris
    Entropy-driven parity-tree selection for low-overhead concurrent error detection in finite state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1547-1554 [Journal]
    
11. Seongmoon Wang, Srimat T. Chakradhar
    A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1555-1564 [Journal]
    
12. Seongmoon Wang, S. K. Gupta
    LT-RTPG: a new test-per-scan BIST TPG for low switching activity. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1565-1574 [Journal]