Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1998, volume: 17, number: 7

1. Koichi Fukuda, Kenji Nishi
   An interpolated flux scheme for cellular automaton device simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:7, pp:553-560 [Journal]
   
2. Ernst Leitner, Siegfried Selberherr
   Mixed-element decomposition method for three-dimensional grid adaptation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:7, pp:561-572 [Journal]
   
3. Harm Arts, Michel R. C. M. Berkelaar, Koen van Eijk
   Computing observability don't cares efficiently through polarization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:7, pp:573-581 [Journal]
   
4. Kevin J. Kerns, Andrew T. Yang
   Preservation of passivity during RLC network reduction via split congruence transformations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:7, pp:582-591 [Journal]
   
5. Daniel R. Brasen, Gabriele Saucier
   Using cone structures for circuit partitioning into FPGA packages. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:7, pp:592-600 [Journal]
   
6. Stan Y. Liao, Srinivas Devadas, Kurt Keutzer
   Code density optimization for embedded DSP processors using data compression techniques. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:7, pp:601-608 [Journal]
   
7. Michael Jünger, Sebastian Leipert, Petra Mutzel
   A note on computing a maximal planar subgraph using PQ-trees. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:7, pp:609-612 [Journal]
   
8. Xiao Quan Li, Marwan A. Jabri
   Machine learning-based VLSI cells shape function estimation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:7, pp:613-623 [Journal]
   
9. A. R. Naseer, M. Balakrishnan, Anshul Kumar
   Direct mapping of RTL structures onto LUT-based FPGA's. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:7, pp:624-631 [Journal]
   
10. Raymond S. Winton, William R. Bandy
    A simple, continuous, analytical charge/capacitance model for the short-channel MOSFET. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:7, pp:631-638 [Journal]