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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1988, volume: 7, number: 7

  1. Steven G. Duvall
    An interchange format for process and device simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:7, pp:741-754 [Journal]
  2. Roberto Guerrieri, Andrew R. Neureuther
    Simulation of microcrack effects in dissolution of positive resist exposed by X-ray lithography. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:7, pp:755-764 [Journal]
  3. Sun Young Hwang, Tom Blank, Kiyoung Choi
    Fast functional simulation: an incremental approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:7, pp:765-774 [Journal]
  4. Corrado Pedron, André Stauffer
    Analysis and synthesis of combinational pass transistor circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:7, pp:775-786 [Journal]
  5. Salim U. Chowdhury, Melvin A. Breuer
    Optimum design of IC power/ground nets subject to reliability constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:7, pp:787-796 [Journal]
  6. Takao Asano
    Generalized Manhattan path algorithm with applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:7, pp:797-804 [Journal]
  7. Shervin Hojat, Richard Y. Kain
    On the simplification of a placement problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:7, pp:805-812 [Journal]
  8. Henry Cox, Janusz Rajski
    A method of fault analysis for test generation and fault diagnosis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:7, pp:813-833 [Journal]
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