The SCEAS System
Navigation Menu

Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2005, volume: 24, number: 4

  1. R. Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein
    Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:502-515 [Journal]
  2. Jianwen Zhu, Silvian Calman
    Context sensitive symbolic pointer analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:516-531 [Journal]
  3. Robert B. Reese, Mitchell A. Thornton, Cherrice Traver, David Hemmendinger
    Early evaluation for performance enhancement in phased logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:532-550 [Journal]
  4. Jingcao Hu, Radu Marculescu
    Energy- and performance-aware mapping for regular NoC architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:551-562 [Journal]
  5. Bikram Baidya, Tamal Mukherjee
    Layout verification for mixed-domain integrated MEMS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:563-577 [Journal]
  6. Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong
    Simultaneous power supply planning and noise avoidance in floorplan design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:578-587 [Journal]
  7. Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao
    The Y architecture for on-chip interconnect: analysis and methodology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:588-599 [Journal]
  8. Sampath Dechu, Zion Cien Shen, Chris C. N. Chu
    An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:600-608 [Journal]
  9. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu
    Buffer planning as an Integral part of floorplanning with consideration of routing congestion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:609-621 [Journal]
  10. Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy
    Finite memory test response compactors for embedded test applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:622-634 [Journal]
  11. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:635-645 [Journal]
  12. Ankur Srivastava, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh
    On effective slack management in postscheduling phase. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:645-653 [Journal]
  13. Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
    On the numerical stability of Green's function for substrate coupling in integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:653-658 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002