Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1991, volume: 10, number: 4

1. Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
   Reduced offsets for minimization of binary-valued functions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:413-426 [Journal]
   
2. Kurt Keutzer, Sharad Malik, Alexander Saldanha
   Is redundancy necessary to reduce delay? [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:427-435 [Journal]
   
3. Bo-Gwan Kim, Donald L. Dietmeyer
   Multilevel logic synthesis of symmetric switching functions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:436-446 [Journal]
   
4. C. Bernard Shung, Rajeev Jain, Ken Rimey, Edward Wang, Mani B. Srivastava, Brian C. Richards, Erik Lettang, Syed Khalid Azim, Lars E. Thon, Paul N. Hilfinger, Jan M. Rabaey, Robert W. Brodersen
   An integrated CAD system for algorithm-specific IC design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:447-463 [Journal]
   
5. Cheng-Tsung Hwang, Jiahn-Humg Lee, Yu-Chin Hsu
   A formal approach to the scheduling problem in high level synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:464-475 [Journal]
   
6. John H. Chan, Andrei Vladimirescu, Xiao-Chun Gao, Peter Liebmann, John Valainis
   Nonlinear transformer model for circuit simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:476-482 [Journal]
   
7. James P. Cohoon, Shailesh U. Hegde, Worthy N. Martin, Dana S. Richards
   Distributed genetic algorithms for the floorplan design problem. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:483-492 [Journal]
   
8. Paul Vanoostende, Paul Six, Hugo De Man
   DARSI: RC data reduction [VLSI simulation]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:493-500 [Journal]
   
9. Walter Allegretto, Arokia Nathan, Henry Baltes
   Numerical analysis of magnetic-field-sensitive bipolar devices. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:501-511 [Journal]
   
10. Gennady S. Gildenblat, Cheng-Liang Huang
    N-channel MOSFET model for the 60-300-K temperature range. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:512-518 [Journal]
    
11. Gerd Krüger
    A tool for hierarchical test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:519-524 [Journal]
    
12. Youssef Saab, Vasant B. Rao
    Combinatorial optimization by stochastic evolution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:525-535 [Journal]
    
13. Khe-Sing The, Martin D. F. Wong, Jason Cong
    A layout modification approach to via minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:536-541 [Journal]
    
14. Reinhard Erwe, Norio Tanabe
    Efficient simulation of MOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:541-544 [Journal]
    
15. Michele Favalli, Piero Olivo, Bruno Riccò
    A novel critical path heuristic for fast fault grading. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:544-548 [Journal]
    
16. Keiho Akiyama, Kewal K. Saluja
    A method of reducing aliasing in a built-in self-test environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:548-553 [Journal]