Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1999, volume: 18, number: 4

1. Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley
   Device-level early floorplanning algorithms for RF circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:375-388 [Journal]
   
2. Kia Bazargan, Samjung Kim, Majid Sarrafzadeh
   Nostradamus: a floorplanner of uncertain designs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:389-397 [Journal]
   
3. Chris C. N. Chu, Martin D. F. Wong
   Greedy wire-sizing is linear time. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:398-405 [Journal]
   
4. Jason Cong, Lei He
   Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:406-420 [Journal]
   
5. Shantanu Dutt, Hasan Arslan, Halim Theny
   Partitioning using second-order information and stochastic-gainfunctions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:421-435 [Journal]
   
6. Huibo Hou, Jiang Hu, Sachin S. Sapatnekar
   Non-Hanan routing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:436-444 [Journal]
   
7. Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky
   Filling algorithms and analyses for layout density control. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:445-462 [Journal]
   
8. Evanthia Papadopoulou, D. T. Lee
   Critical area computation via Voronoi diagrams. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:463-474 [Journal]
   
9. Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
   A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:475-483 [Journal]
   
10. Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng
    Sequence-pair approach for rectilinear module placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:484-493 [Journal]
    
11. Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas
    An algorithm for determining repetitive patterns in very large IC layouts. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:494-501 [Journal]