The SCEAS System
Navigation Menu

Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2002, volume: 21, number: 12

  1. Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, Malay K. Ganai
    Robust Boolean reasoning for equivalence checking and functional property verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1377-1394 [Journal]
  2. Cagdas Akturan, Margarida F. Jacome
    RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1395-1415 [Journal]
  3. Tzyy-Kuen Tien, Shih-Chieh Chang, Tong-Kai Tsai
    Crosstalk alleviation for dynamic PLAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1416-1424 [Journal]
  4. Wim Schoenmaker, Wim Magnus, Peter Meuris, Bert Maleszka
    Renormalization group meshes and the discretization of TCAD equations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1425-1433 [Journal]
  5. Ting-Yuan Wang, Charlie Chung-Ping Chen
    3-D Thermal-ADI: a linear-time chip level transient thermal simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1434-1445 [Journal]
  6. Emil Gizdarski, Hideo Fujiwara
    SPIRIT: a highly robust combinational test generation algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1446-1458 [Journal]
  7. Piotr R. Sidorowicz, Janusz A. Brzozowski
    A framework for testing special-purpose memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1459-1468 [Journal]
  8. Andreas G. Veneris, Magdy S. Abadir
    Design rewiring using ATPG. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1469-1479 [Journal]
  9. Maciej J. Ciesielski, Serkan Askar, Samuel Levitin
    Analytical approach to layout generation of datapath cells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1480-1488 [Journal]
  10. Yungseon Eo, Seongkyun Shin, William R. Eisenstadt, Jongin Shim
    Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicoupled transmission line system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1489-1497 [Journal]
  11. Xiaofang Gao, Juin J. Liou, Joe Bernier, Gregg Croft, Adelmo Ortiz-Conde
    Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1497-1502 [Journal]
  12. Keerthi Heragu, Manish Sharma, Rahul Kundu, Ronald D. Blanton
    Test vector generation for charge sharing failures in dynamic logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1502-1508 [Journal]
  13. Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim
    Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1509-1517 [Journal]
  14. Sandeep Koranne
    Formulating SoC test scheduling as a network transportation problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1517-1525 [Journal]
  15. In-Cheol Park, Hyeong-Ju Kang
    Digital filter synthesis based on an algorithm to generate all minimal signed digit representations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1525-1529 [Journal]
  16. Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri
    Design of hierarchical cellular automata for on-chip test pattern generator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1530-1539 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002