Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1995, volume: 14, number: 11

1. Ting-Wei Tang, Mei-Kei Ieong
   Discretization of flux densities in device simulations using optimum artificial diffusivity. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1309-1315 [Journal]
   
2. Maurizio Damiani, Jerry Chih-Yuan Yang, Giovanni De Micheli
   Optimization of combinational logic circuits based on compatible gates. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1316-1327 [Journal]
   
3. Mitchell A. Thornton, V. S. S. Nair
   Efficient calculation of spectral coefficients and their applications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1328-1341 [Journal]
   
4. Charles J. Alpert, Andrew B. Kahng
   Multiway partitioning via geometric embeddings, orderings, and dynamic programming. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1342-1358 [Journal]
   
5. Qinghong Wu, C. Y. Roger Chen, Bradley S. Carlson
   LILA: layout generation for iterative logic arrays. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1359-1369 [Journal]
   
6. Jau-Shien Chang, Chen-Shang Lin
   Test set compaction for combinational circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1370-1378 [Journal]
   
7. Jacob Savir
   Shrinking wide compressors [BIST]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1379-1387 [Journal]
   
8. Murali M. R. Gala, Don E. Ross, Karan L. Watson, Beena Vasudevan, Peter Utama
   Built-in self test for C-testable ILA's. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1388-1398 [Journal]
   
9. Owen Kaser
   On squashing hierarchical designs [VLSI]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1398-1402 [Journal]
   
10. Jien-Chung Lo, James C. Daly, Michael Nicolaidis
    A strongly code disjoint built-in current sensor for strongly fault-secure static CMOS realizations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1402-1407 [Journal]
    
11. Anand Raghunathan, Pranav Ashar, Sharad Malik
    Test generation for cyclic combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1408-1414 [Journal]