Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1990, volume: 9, number: 10

1. TingTing Hwang, Robert Michael Owens, Mary Jane Irwin
   Exploiting communication complexity for multilevel logic synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:10, pp:1017-1027 [Journal]
   
2. Asim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili
   A module generator for optimized CMOS buffers. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:10, pp:1028-1046 [Journal]
   
3. Evangelos Simoudis
   Learning redesign knowledge circuit redesign. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:10, pp:1047-1062 [Journal]
   
4. Patrick Odent, Luc J. M. Claesen, Hugo De Man
   Acceleration of relaxation-based circuit simulation using a multiprocessor system. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:10, pp:1063-1072 [Journal]
   
5. Jonathan Rose
   Parallel global routing for standard cells. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:10, pp:1085-1095 [Journal]
   
6. Raja Venkateswaran, Pinaki Mazumder
   A hexagonal array machine for multilayer wire routing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:10, pp:1096-1112 [Journal]
   
7. E. Rorris, R. R. O'Brien, F. F. Morehead, R. F. Lever, J. P. Peng, G. R. Srinivasan
   A new approach to the simulation of the coupled point defects and impurity diffusion. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:10, pp:1113-1122 [Journal]
   
8. Gregory Munson Yeric, A. F. Tasch Jr., Sanjay K. Banerjee
   A universal MOSFET mobility degradation model for circuit simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:10, pp:1123-1126 [Journal]
   
9. Jacques Benkoski, E. Vanden Meersch, Luc J. M. Claesen, Hugo De Man
   Timing verification using statically sensitizable paths. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:10, pp:10723-10784 [Journal]