Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2001, volume: 20, number: 5

1. Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap
   RC delay metrics for performance optimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:571-582 [Journal]
   
2. Evanthia Papadopoulou
   Critical area computation for missing material defects in VLSIcircuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:583-597 [Journal]
   
3. Chin-Chih Chang, Jason Cong
   Pseudopin assignment with crosstalk noise control. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:598-611 [Journal]
   
4. Lauren Hui Chen, Malgorzata Marek-Sadowska
   Aggressor alignment for worst-case crosstalk noise. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:612-621 [Journal]
   
5. Christoph Albrecht
   Global routing by new approximation algorithms for multicommodityflow. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:622-632 [Journal]
   
6. Jason Cong, Jie Fang, Kei-Yong Khoo
   DUNE-a multilayer gridless routing system. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:633-647 [Journal]
   
7. Andrew B. Kahng, Stefanus Mantik, Dirk Stroobandt
   Toward accurate models of achievable routing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:648-659 [Journal]
   
8. Probir Sarkar, Cheng-Kok Koh
   Routability-driven repeater block planning for interconnect-centricfloorplanning. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:660-671 [Journal]
   
9. Rony Kay, Rob A. Rutenbar
   Wire packing - a strong formulation of crosstalk-aware chip-leveltrack/layer assignment with an efficient integer programming solution. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:672-679 [Journal]
   
10. Yu-Yen Mo, Chris C. N. Chu
    Hybrid dynamic/quadratic programming algorithm for interconnecttree optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:680-686 [Journal]
    
11. Evangeline F. Y. Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong
    Handling soft modules in general nonslicing floorplan usingLagrangian relaxation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:687-692 [Journal]
    
12. Hai Zhou, Adnan Aziz
    Buffer minimization in pass transistor logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:693-697 [Journal]