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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2003, volume: 22, number: 3

  1. Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky
    Minimum buffered routing with bounded capacitive load for slew rate and reliability control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:241-253 [Journal]
  2. Mary Y. L. Wisniewski, Emmanuel Yashchin, Robert L. Franch, David P. Conrady, Daniel N. Maynard, Giovanni Fiorenza, I. Cevdet Noyan
    The physical design of on-chip interconnections. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:254-276 [Journal]
  3. Sheldon X.-D. Tan, C.-J. Richard Shi
    Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:277-284 [Journal]
  4. Clemens Heitzinger, Wolfgang Pyka, Naoki Tamaoki, Toshiro Takase, Toshimitsu Ohmine, Siegfried Selberherr
    Simulation of arsenic in situ doping with polysilicon CVD and its application to high aspect ratio trenches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:285-292 [Journal]
  5. Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
    Reverse-order-restoration-based static test compaction for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:293-304 [Journal]
  6. Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas
    Exact path delay fault coverage with fundamental ZBDD operations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:305-316 [Journal]
  7. Kianosh Rahimi, Mani Soma
    Layout driven synthesis of multiple scan chains. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:317-326 [Journal]
  8. Yuejian Wu, Paul N. MacDonald
    Testing ASICs with multiple identical cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:327-336 [Journal]
  9. Murat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj
    Early probabilistic noise estimation for capacitively coupled interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:337-345 [Journal]
  10. Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria
    Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:346-351 [Journal]
  11. Anshuman Chandra, Krishnendu Chakrabarty
    A unified approach to reduce SOC test data volume, scan power and testing time. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:352-363 [Journal]
  12. Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee
    Test pattern generation and clock disabling for simultaneous test time and power reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:363-370 [Journal]
  13. James F. Plusquellic, Abhishek Singh, Chintan Patel, Anne E. Gattiker
    Power supply transient signal analysis for defect-oriented test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:370-374 [Journal]
  14. Qiushuang Zhang, Ian G. Harris
    Partial BIST insertion to eliminate data correlation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:374-379 [Journal]
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