Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1996, volume: 15, number: 12

1. Zeyi Wang, Yanhong Yuan, Qiming Wu
   A parallel multipole accelerated 3-D capacitance simulator based on an improved model. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1441-1450 [Journal]
   
2. Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi
   Automatic state space decomposition for approximate FSM traversal based on circuit analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1451-1464 [Journal]
   
3. Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Bernard Plessier, Fabio Somenzi
   Algorithms for approximate FSM traversal based on state space decomposition. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1465-1478 [Journal]
   
4. Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
   Markovian analysis of large finite state machines. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1479-1493 [Journal]
   
5. Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng
   Perturb and simplify: multilevel Boolean network optimizer. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1494-1504 [Journal]
   
6. Michael J. Alexander, Gabriel Robins
   New performance-driven FPGA routing algorithms. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1505-1517 [Journal]
   
7. Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani
   VLSI module placement based on rectangle-packing by the sequence-pair. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1518-1524 [Journal]
   
8. Weiping Shi
   A fast algorithm for area minimization of slicing floorplans. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1525-1532 [Journal]
   
9. Hannah Honghua Yang, Martin D. F. Wong
   Balanced partitioning. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1533-1540 [Journal]
   
10. Martin Bächtold, Jan G. Korvink, Henry Baltes
    Enhanced multipole acceleration technique for the solution of large Poisson computations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1541-1546 [Journal]
    
11. Yun Sik Lee, Peter M. Maurer
    Bit-parallel multidelay simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1547-1554 [Journal]
    
12. Haluk Konuk, F. Joel Ferguson, Tracy Larrabee
    Charge-based fault simulation for CMOS network breaks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1555-1567 [Journal]
    
13. Chih-Ang Chen, Sandeep K. Gupta
    Design of efficient BIST test pattern generators for delay testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1568-1575 [Journal]
    
14. Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
    Pin assignment with global routing for VLSI building block layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1575-1583 [Journal]
    
15. Tsung-Yi Wu, Youn-Long Lin
    Register minimization beyond sharing among variables. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1583-1587 [Journal]
    
16. Shujian Zhang, D. Michael Miller, Jon C. Muzio
    Notes on "Complexity of the lookup-table minimization problem for FPGA technology mapping". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1588-1590 [Journal]