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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1999, volume: 18, number: 9

  1. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev
    Decomposition and technology mapping of speed-independent circuits using Boolean relations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1221-1236 [Journal]
  2. Morgan Enos, Scott Hauck, Majid Sarrafzadeh
    Evaluation and optimization of replication algorithms for logic bipartitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1237-1248 [Journal]
  3. Naresh Maheshwari, Sachin S. Sapatnekar
    Optimizing large multiphase level-clocked circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1249-1264 [Journal]
  4. Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky
    On wirelength estimations for row-based placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1265-1278 [Journal]
  5. Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta
    Extraction of functional regularity in datapath circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1279-1296 [Journal]
  6. Chris C. N. Chu, Martin D. F. Wong
    An efficient and optimal algorithm for simultaneous buffer and wire sizing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1297-1304 [Journal]
  7. Amir H. Salek, Jinan Lou, Massoud Pedram
    An integrated logical and physical design flow for deep submicron circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1305-1315 [Journal]
  8. Darko Kirovski, Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith
    Application-driven synthesis of memory-intensive systems-on-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1316-1326 [Journal]
  9. Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie
    Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1327-1340 [Journal]
  10. Shi-Yu Huang, Kwang-Ting Cheng
    ErrorTracer: design error diagnosis based on fault simulation techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1341-1352 [Journal]
  11. Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich
    Analog testing by characteristic observation inference. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1353-1368 [Journal]
  12. Massimo Alioto, Gaetano Palumbo
    Highly accurate and simple models for CML and ECL gates. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1369-1375 [Journal]
  13. Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
    AutoFix: a hybrid tool for automatic logic rectification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1376-1384 [Journal]
  14. Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang
    Slicing floorplans with boundary constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1385-1389 [Journal]
  15. Jason Y. Zien, Martine D. F. Schlag, Pak K. Chan
    Multilevel spectral hypergraph partitioning with arbitrary vertex sizes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1389-1399 [Journal]
  16. K. C. Chang
    Comment on "Event suppression by optimizing VHDL programs". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1400-1401 [Journal]
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