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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1990, volume: 9, number: 2

  1. Han Young Koh, Carlo H. Séquin, Paul R. Gray
    OPASYN: a compiler for CMOS operational amplifiers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:113-125 [Journal]
  2. Don Stark, Mark Horowitz
    Techniques for calculating currents and voltages in VLSI power supply networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:126-132 [Journal]
  3. Genhong Ruan, Jiri Vlach, James A. Barby
    Logic simulation with current-limited switches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:133-141 [Journal]
  4. Gregory T. Brauns, R. J. Bishop, Michael Steer, John J. Paulos, Sasan H. Ardalan
    Table-based modeling of delta-sigma modulators using ZSIM. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:142-150 [Journal]
  5. Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
    Hybrid routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:151-157 [Journal]
  6. Kurt Mehlhorn, Stefan Näher
    A faster compaction algorithm with automatic jog insertion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:158-166 [Journal]
  7. Hyunchul Shin, Alberto L. Sangiovanni-Vincentelli, Carlo H. Séquin
    'Zone-refining' techniques for IC layout compaction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:167-179 [Journal]
  8. Michael Kaufmann
    A linear-time algorithm for routing in a convex grid. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:180-184 [Journal]
  9. Jan-Ming Ho, Gopalakrishnan Vijayan, Chak-Kuen Wong
    New algorithms for the rectilinear Steiner tree problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:185-193 [Journal]
  10. Ronald F. Ayres
    Completely automatic completion of VLSI designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:194-202 [Journal]
  11. Sunggu Lee, Kang G. Shin
    Design for test using partial parallel scan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:203-211 [Journal]
  12. Fadi Maamari, Janusz Rajski
    A method of fault simulation based on stem regions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:212-220 [Journal]
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