Don Stark, Mark Horowitz Techniques for calculating currents and voltages in VLSI power supply networks. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:126-132 [Journal]
Kurt Mehlhorn, Stefan Näher A faster compaction algorithm with automatic jog insertion. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:158-166 [Journal]
Michael Kaufmann A linear-time algorithm for routing in a convex grid. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:180-184 [Journal]
Ronald F. Ayres Completely automatic completion of VLSI designs. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:194-202 [Journal]
Sunggu Lee, Kang G. Shin Design for test using partial parallel scan. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:203-211 [Journal]
Fadi Maamari, Janusz Rajski A method of fault simulation based on stem regions. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:212-220 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP