Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2003, volume: 22, number: 11

1. Cesare Alippi, Andrea Galbusera, Marco Stellini
   An application-level synthesis methodology for multidimensional embedded processing systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1457-1470 [Journal]
   
2. Peter M. Maurer
   Efficient event-driven simulation by exploiting the output observability of gate clusters. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1471-1486 [Journal]
   
3. Junhyung Um, Taewhan Kim
   Synthesis of arithmetic circuits considering layout effects. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1487-1503 [Journal]
   
4. Alex Doboli, Ranga Vemuri
   Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1504-1520 [Journal]
   
5. Guoan Zhong, Cheng-Kok Koh, Kaushik Roy
   On-chip interconnect modeling by wire duplication. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1521-1532 [Journal]
   
6. Haihua Su, Kaushik Gala, Sachin S. Sapatnekar
   Analysis and optimization of structured power/ground networks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1533-1544 [Journal]
   
7. Yu-Min Lee, Charlie Chung-Ping Chen
   The power grid transient simulation in linear time based on 3-D alternating-direction-implicit method. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1545-1550 [Journal]
   
8. Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
   Hierarchical whitespace allocation in top-down placement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1550-1556 [Journal]
   
9. Alex Doboli, Ranga Vemuri
   Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1556-1568 [Journal]
   
10. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
    Addressing useless test data in core-based system-on-a-chip test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1568-1580 [Journal]
    
11. Soha Hassoun, Charles J. Alpert
    Optimal path routing in single- and multiple-clock domain systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1580-1588 [Journal]
    
12. Alan Mishchenko
    Fast computation of symmetries in Boolean functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1588-1593 [Journal]