Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2000, volume: 19, number: 10

1. Henrik Hulgaard, Tod Amon
   Symbolic timing analysis of asynchronous systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1093-1104 [Journal]
   
2. Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana
   Integrating variable-latency components into high-level synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1105-1117 [Journal]
   
3. Christopher S. Helvig, Gabriel Robins, Alexander Zelikovsky
   New approximation algorithms for routing with multiport terminals. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1118-1128 [Journal]
   
4. Ion I. Mandoiu, Vijay V. Vazirani, Joseph L. Ganley
   A new heuristic for rectilinear Steiner trees. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1129-1139 [Journal]
   
5. Maogang Wang, Xiaojian Yang, Majid Sarrafzadeh
   Congestion minimization during placement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1140-1148 [Journal]
   
6. Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
   Sequential synthesis using S1S. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1149-1162 [Journal]
   
7. Krishnendu Chakrabarty
   Test scheduling for core-based systems using mixed-integer linearprogramming. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1163-1174 [Journal]
   
8. Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer
   Automated synthesis of phase shifters for built-in self-testapplications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1175-1188 [Journal]
   
9. Pramodchandran N. Variyam, Abhijit Chatterjee
   Specification-driven test generation for analog circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1189-1201 [Journal]
   
10. Seungjoon Park, Satyaki Das, David L. Dill
    Automatic checking of aggregation abstractions through stateenumeration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1202-1210 [Journal]
    
11. Yi-Kan Cheng, Sung-Mo Kang
    A temperature-aware simulation environment for reliable ULSI chipdesign. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1211-1220 [Journal]
    
12. Haksu Kim, Dian Zhou
    Efficient implementation of a planar clock routing with thetreatment of obstacles. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1220-1225 [Journal]
    
13. Aiguo Xie, Peter A. Beerel
    Implicit enumeration of strongly connected components and anapplication to formal verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1225-1230 [Journal]