Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2001, volume: 20, number: 2

1. Praveen K. Murthy, Shuvra S. Bhattacharyya
   Shared buffer implementations of signal processing systems usinglifetime analysis techniques. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:177-198 [Journal]
   
2. Sanghun Park, Kiyoung Choi
   Performance-driven high-level synthesis with bit-level chaining andclock selection. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:199-212 [Journal]
   
3. Luc Séméria, Giovanni De Micheli
   Resolution, optimization, and encoding of pointer variables for thebehavioral synthesis from C. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:213-233 [Journal]
   
4. Markus Weinhardt, Wayne Luk
   Pipeline vectorization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:234-248 [Journal]
   
5. Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton
   Theory of safe replacements for sequential circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:249-265 [Journal]
   
6. Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang
   Charge-sharing alleviation and detection for CMOS domino circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:266-280 [Journal]
   
7. Pei-Ning Guo, Toshihiko Takahashi, Chung-Kuan Cheng, Takeshi Yoshimura
   Floorplanning using a tree representation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:281-289 [Journal]
   
8. Hyungwon Kim, John P. Hayes
   Realization-independent ATPG for designs with unimplemented blocks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:290-306 [Journal]
   
9. Khaled Saab, Naim Ben Hamida, Bozena Kaminska
   Closing the gap between analog and digital testing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:307-314 [Journal]
   
10. Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah, John P. Hayes
    Fast and accurate timing characterization using functionalinformation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:315-331 [Journal]
    
11. Adnan Aziz, James H. Kukula, Thomas R. Shiple, Jun Yuan
    Efficient control state-space search. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:332-336 [Journal]
    
12. Irith Pomeranz, Sudhakar M. Reddy
    Vector replacement to improve static-test compaction forsynchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:336-342 [Journal]
    
13. Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Kun-Lin Tsai
    A bipartition-codec architecture to reduce power in pipelinedcircuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:343-348 [Journal]