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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1999, volume: 18, number: 10

  1. Yanbing Li, Wayne Wolf
    Hardware/software co-synthesis with memory hierarchies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1405-1417 [Journal]
  2. Wei-Chun Chou, Peter A. Beerel, Kenneth Y. Yun
    Average-case technology mapping of asynchronous burst-mode circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1418-1434 [Journal]
  3. Hoan H. Pham, Arokia Nathan
    An integral equation of the second kind for computation of capacitance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1435-1441 [Journal]
  4. Le-Chin Eugene Liu, Carl Sechen
    Multilayer chip-level global routing using an efficient graph-based Steiner tree heuristic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1442-1451 [Journal]
  5. Le-Chin Eugene Liu, Carl Sechen
    Multilayer pin assignment for macro cell circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1452-1461 [Journal]
  6. Hsiao-Ping Tseng, Carl Sechen
    A gridless multilayer router for standard cell circuits using CTMcells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1462-1479 [Journal]
  7. Gerard A. Allan, Anthony J. Walton
    Efficient extra material critical area algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1480-1486 [Journal]
  8. Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai
    Fault emulation: A new methodology for fault grading. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1487-1495 [Journal]
  9. Sujit Dey, Anand Raghunathan, Niraj K. Jha, Kazutoshi Wakabayashi
    Controller-based power management for control-flow intensive designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1496-1508 [Journal]
  10. Mahesh B. Patil
    Extension of the VR discretization scheme for velocity saturation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1508-1511 [Journal]
  11. Massoud Pedram, Bryan Preas
    Interconnection analysis for standard cell layouts. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1512-1519 [Journal]
  12. Jin-Tai Yan
    An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1519-1526 [Journal]
  13. Robert P. Dick, Niraj K. Jha
    Corrections to "mogac: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1527-1527 [Journal]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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