The SCEAS System
Navigation Menu

Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1992, volume: 11, number: 11

  1. Thang Nguyen Bui, Willie Hsu, SingLing Lee
    A 2.5 approximation algorithm for the multi-via assignment problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1325-1333 [Journal]
  2. Ze-Yi Wang, Ke-Chih Wu, Robert W. Dutton
    An approach to construct pre-conditioning matrices for block iteration of linear equations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1334-1343 [Journal]
  3. Carlos H. Díaz, Sung-Mo Kang
    New algorithms for circuit simulation of device breakdown. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1344-1354 [Journal]
  4. Gerard A. Allan, Anthony J. Walton, Robert J. Holwill
    A yield improvement technique for IC layout using local design rules. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1355-1362 [Journal]
  5. Tom Chanak, Rakesh Chadha, Kishore Singhal
    Switched-capacitor simulation models for full-chips verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1363-1371 [Journal]
  6. Colin Gordon, Thomas Blazeck, Raj Mittra
    Time-domain simulation of multiconductor transmission lines with frequency-dependent losses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1372-1387 [Journal]
  7. Cheryl Harkness, Daniel P. Lopresti
    Interval methods for modeling uncertainty in RC timing analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1388-1401 [Journal]
  8. J. Paul Harvey, Mohamed I. Elmasry, Bosco Leung
    STAIC: an interactive framework for synthesizing CMOS and BiCMOS analog circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1402-1417 [Journal]
  9. James A. Power, W. A. Lane
    An enhanced SPICE MOSFET model suitable for analog applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1418-1425 [Journal]
  10. Peter Vanbekbergen, Gert Goossens, Francky Catthoor, Hugo De Man
    Optimized synthesis of asynchronous control circuits from graph-theoretic specifications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1426-1438 [Journal]
  11. Vijay S. Iyengar, Gopalakrishnan Vijayan
    Optimized test application timing for AC test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1439-1449 [Journal]
  12. Michel Renovell, Gaston Cambon
    Electrical analysis and modeling of floating-gate fault. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1450-1458 [Journal]
  13. Michele Favalli, Piero Olivo, Bruno Riccò
    A probabilistic fault model for `analog' faults in digital CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1459-1462 [Journal]
  14. Andrew B. Kahng, Gabriel Robins
    On the performance bounds for a class of rectilinear Steiner tree heuristics in arbitrary dimension. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1462-1465 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002