Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1994, volume: 13, number: 10

1. Konrad Doll, Frank M. Johannes, Kurt Antreich
   Iterative placement improvement by network flow methods. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1189-1200 [Journal]
   
2. King C. Ho, Sarma B. K. Vrudhula
   Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1201-1222 [Journal]
   
3. Ping-Chung Li, Georgios I. Stamoulis, Ibrahim N. Hajj
   A probabilistic timing approach to hot-carrier effect estimation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1223-1234 [Journal]
   
4. Minchang Liang, Mark E. Law
   An object-oriented approach to device simulation-FLOODS. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1235-1240 [Journal]
   
5. Dwight L. Woolard, Hong Tian, Michael A. Littlejohn, K. W. Kim
   The implementation of physical boundary conditions in the Monte Carlo simulation of electron devices. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1241-1246 [Journal]
   
6. Walter Allegretto, Bing Shen, P. Haswell, Zhongsheng Lai, Alexander M. Robinson
   Numerical modeling of a micromachined thermal conductivity gas pressure sensor. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1247-1256 [Journal]
   
7. Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage
   Time-domain macromodels for VLSI interconnect analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1257-1270 [Journal]
   
8. Abdolreza Nabavi-Lishi, Nicholas C. Rumin
   Inverter models of CMOS gates for supply current and delay evaluation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1271-1279 [Journal]
   
9. TingTing Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo-Hua Wang
   Logic synthesis for field-programmable gate arrays. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1280-1287 [Journal]
   
10. Jaushin Lee, Janak H. Patel
    Architectural level test generation for microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1288-1300 [Journal]
    
11. T. V. Nguyen
    Recursive convolution and discrete time domain simulation of lossy coupled transmission lines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1301-1305 [Journal]