Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2003, volume: 22, number: 4

1. Charles J. Alpert, Sachin S. Sapatnekar
   Guest editorial. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:385-386 [Journal]
   
2. Ulrich Brenner, André Rohe
   An effective congestion-driven placement framework. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:387-394 [Journal]
   
3. Chin-Chih Chang, Jason Cong, David Zhigang Pan, Xin Yuan
   Multilevel global placement with congestion control. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:395-409 [Journal]
   
4. Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh
   Routability-driven white space allocation for fixed-die standard-cell placement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:410-419 [Journal]
   
5. Yongseok Cheon, Martin D. F. Wong
   Design hierarchy-guided multilevel circuit partitioning. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:420-427 [Journal]
   
6. Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif
   Optimal decoupling capacitor sizing and placement for standard-cell layout designs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:428-436 [Journal]
   
7. Prashant Saxena, Satyanarayan Gupta
   On integrating power and signal routing for shield count minimization in congested regions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:437-445 [Journal]
   
8. Shuo Zhang, Wayne Wei-Ming Dai
   TEG: a new post-layout optimization method. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:446-456 [Journal]
   
9. Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen
   Twin binary sequences: a nonredundant representation for general nonslicing floorplan. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:457-469 [Journal]
   
10. Chiu-Wing Sham, Evangeline F. Y. Young
    Routability-driven floorplanner with buffer block planning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:470-480 [Journal]
    
11. Milos Hrkic, John Lillis
    Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:481-491 [Journal]
    
12. Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham
    Buffer insertion with adaptive blockage avoidance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:492-498 [Journal]
    
13. Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
    Global and local congestion optimization in technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:498-505 [Journal]
    
14. Seokjin Lee, Martin D. F. Wong
    Timing-driven routing for FPGAs based on Lagrangian relaxation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:506-510 [Journal]