Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2000, volume: 19, number: 2

1. Martin D. F. Wong, Dwight D. Hill
   Editorial. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:173-174 [Journal]
   
2. Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Huijuan Wang, Alexander Zelikovsky
   Optimal phase conflict removal for layout of dark field alternatingphase shifting masks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:175-187 [Journal]
   
3. Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai
   Timing optimization on routed designs with incremental placementand routing characterization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:188-196 [Journal]
   
4. Danqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo Kang
   Interconnect thermal modeling for accurate simulation of circuittiming and reliability. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:197-205 [Journal]
   
5. Wei Chen, Cheng-Ta Hsieh, Massoud Pedram
   Simultaneous gate sizing and placement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:206-214 [Journal]
   
6. Jason Cong, Jie Fang, Kei-Yong Khoo
   Via design rule consideration in multilayer maze routing algorithms. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:215-223 [Journal]
   
7. Kunihiro Fujiyoshi, Hiroshi Murata
   Arbitrary convex and concave rectilinear block packing usingsequence-pair. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:224-233 [Journal]
   
8. Sung-Woo Hur, Ashok Jagannathan, John Lillis
   Timing-driven maze routing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:234-241 [Journal]
   
9. Dennis Sylvester, Kurt Keutzer
   A global wiring paradigm for deep submicron design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:242-252 [Journal]
   
10. Ching-Han Tsai, Sung-Mo Kang
    Cell-level placement for improving substrate thermal distribution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:253-266 [Journal]
    
11. Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Hypergraph partitioning with fixed vertices [VLSI CAD]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:267-272 [Journal]
    
12. Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang
    Slicing floorplans with range constraint. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:272-278 [Journal]