Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2005, volume: 24, number: 1

1. Andrei Radulescu, John Dielissen, Santiago González Pestana, Om Prakash Gangwal, Edwin Rijpkema, Paul Wielage, Kees G. W. Goossens
   An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:4-17 [Journal]
   
2. Kihwan Choi, Ramakrishna Soma, Massoud Pedram
   Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:18-28 [Journal]
   
3. Pietro Babighian, Luca Benini, Enrico Macii
   A scalable algorithm for RTL insertion of gated clocks based on ODCs computation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:29-42 [Journal]
   
4. Joel R. Phillips, Luis Miguel Silveira
   Poor man's TBR: a simple model reduction scheme. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:43-55 [Journal]
   
5. Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury
   ADAMIN: automated, accurate macromodeling of digital aggressors for power and ground supply noise prediction. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:56-64 [Journal]
   
6. Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
   Digital ground bounce reduction by supply current shaping and clock frequency Modulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:65-76 [Journal]
   
7. Saravanan Padmanaban, Spyros Tragoudas
   Efficient identification of (critical) testable path delay faults using decision diagrams. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:77-87 [Journal]
   
8. Antonis M. Paschalis, Dimitris Gizopoulos
   Effective software-based self-test strategies for on-line periodic testing of embedded processors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:88-99 [Journal]
   
9. Alberto La Rosa, Luciano Lavagno, Claudio Passerone
   Implementation of a UMTS turbo decoder on a dynamically reconfigurable platform. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:100-106 [Journal]
   
10. Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha
    Threshold network synthesis and optimization and its application to nanotechnologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:107-118 [Journal]
    
11. Christoph Grimm, Wilhelm Heupke, Klaus Waldschmidt
    Analysis of mixed-signal systems with affine arithmetic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:118-123 [Journal]