Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1998, volume: 17, number: 1

1. Andrew B. Kahng, Majid Sarrafzadeh
   Guest Editorial. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:1, pp:1-2 [Journal]
   
2. Charles J. Alpert, Tony F. Chan, Andrew B. Kahng, Igor L. Markov, Pep Mulet
   Faster minimization of linear wirelength for global placement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:1, pp:3-13 [Journal]
   
3. Jeffrey L. Burns, Jack A. Feldman
   C5M-a control-logic layout synthesis system for high-performance microprocessors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:1, pp:14-23 [Journal]
   
4. Jason Cong, Andrew B. Kahng, Kwok-Shing Leung
   Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:1, pp:24-39 [Journal]
   
5. Rony Kay, Lawrence T. Pileggi
   EWA: efficient wiring-sizing algorithm for signal nets and clock nets. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:1, pp:40-49 [Journal]
   
6. Huiqun Liu, Martin D. F. Wong
   Network-flow-based multiway partitioning with area and pin constraints. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:1, pp:50-59 [Journal]
   
7. Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko
   VLSI/PCB placement with obstacles based on sequence pair. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:1, pp:60-68 [Journal]