Pradip Mandal, V. Visvanathan CMOS op-amp sizing using a geometric programming formulation. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:22-38 [Journal]
Mayukh Bhattacharya, Pinaki Mazumder Augmentation of SPICE for simulation of circuits containingresonant tunneling diodes. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:39-50 [Journal]
Kamal S. Khouri, Niraj K. Jha Clock selection for performance optimization of control-flowintensive behaviors. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:158-165 [Journal]
Yun-Che Wen, Kuen-Jong Lee Analysis and generation of control and observation structures foranalog circuits. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:165-171 [Journal]
Yi-Jong Yeh, Sy-Yen Kuo, Jing-Yang Jou Converter-free multiple-voltage scaling techniques for low-powerCMOS digital design. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:172-176 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP