The SCEAS System
Navigation Menu

Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2001, volume: 20, number: 1

  1. Maria del Mar Hershenson, Stephen P. Boyd, Thomas H. Lee
    Optimal design of a CMOS op-amp via geometric programming. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:1-21 [Journal]
  2. Pradip Mandal, V. Visvanathan
    CMOS op-amp sizing using a geometric programming formulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:22-38 [Journal]
  3. Mayukh Bhattacharya, Pinaki Mazumder
    Augmentation of SPICE for simulation of circuits containingresonant tunneling diodes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:39-50 [Journal]
  4. Rolf Drechsler, Wolfgang Günther, Fabio Somenzi
    Using lower bounds during dynamic BDD minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:51-57 [Journal]
  5. Hirendu Vaishnav, Massoud Pedram
    Alphabetic trees-theory and applications in layout-driven logicsynthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:58-69 [Journal]
  6. Michael W. Beattie, Byron Krauter, Lale Alatan, Lawrence T. Pileggi
    Equipotential shells for efficient inductance extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:70-79 [Journal]
  7. Mohamed Hafed, Mourad Oulmane, Nicholas C. Rumin
    Delay and current estimation in a CMOS inverter with an RC load. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:80-89 [Journal]
  8. Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay
    Interconnect synthesis without wire tapering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:90-104 [Journal]
  9. Tom J. Smy, David J. Walkey, Steven K. Dew
    A 3D thermal simulation tool for integrated devices-Atar. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:105-115 [Journal]
  10. André Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand
    On the detectability of CMOS floating gate transistor faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:116-128 [Journal]
  11. Wendy Belluomini, Chris J. Myers, H. Peter Hofstee
    Timed circuit verification using TEL structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:129-146 [Journal]
  12. Shih-Chieh Chang, Jiann-Chyi Rau
    A timing-driven pseudoexhaustive testing for VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:147-158 [Journal]
  13. Kamal S. Khouri, Niraj K. Jha
    Clock selection for performance optimization of control-flowintensive behaviors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:158-165 [Journal]
  14. Yun-Che Wen, Kuen-Jong Lee
    Analysis and generation of control and observation structures foranalog circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:165-171 [Journal]
  15. Yi-Jong Yeh, Sy-Yen Kuo, Jing-Yang Jou
    Converter-free multiple-voltage scaling techniques for low-powerCMOS digital design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:172-176 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002