Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2002, volume: 21, number: 4

1. Paolo Crippa, Claudio Turchetti, Massimo Conti
   A statistical methodology for the design of high-performance CMOScurrent-steering digital-to-analog converters. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:377-394 [Journal]
   
2. Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
   Circuit simplification for the symbolic analysis of analogintegrated circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:395-407 [Journal]
   
3. Cheng-Ta Hsieh, Massoud Pedram
   Architectural energy optimization by bus splitting. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:408-414 [Journal]
   
4. Nestoras E. Evmorfopoulos, Georgios I. Stamoulis, John N. Avaritsiotis
   A Monte Carlo approach for maximum power estimation based onextreme value theory. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:415-432 [Journal]
   
5. José Luis Rosselló, Jaume Segura
   Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:433-448 [Journal]
   
6. Der-Cheng Huang, Wen-Ben Jone
   A parallel built-in self-diagnostic method for embedded memoryarrays. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:449-465 [Journal]
   
7. Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
   On automatic-verification pattern generation for SoC withport-order fault model. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:466-479 [Journal]
   
8. Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
   Fault simulation and test algorithm generation for random accessmemories. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:480-490 [Journal]
   
9. Wai-Kei Mak
   Min-cut partitioning with functional replication fortechnology-mapped circuits using minimum area overhead. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:491-497 [Journal]
   
10. Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay
    Correction to "interconnect synthesis without wire tapering". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:497-497 [Journal]