Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2001, volume: 20, number: 4

1. Siddharth Rele, Vipin Jain, Santosh Pande, J. Ramanujam
   Compact and efficient code generation through program restructuringon limited memory embedded DSPs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:477-494 [Journal]
   
2. Yutao Ma, Litian Liu, Lilin Tian, Zhiping Yu, Zhijian Li
   Analytical charge-control and I-V model for submicrometer anddeep-submicrometer MOSFETs fully comprising quantum mechanical effects. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:495-502 [Journal]
   
3. Prashant Saxena, C. L. Liu
   Optimization of the maximum delay of global interconnects duringlayer assignment. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:503-515 [Journal]
   
4. Lixin Su, Wray L. Buntine, A. Richard Newton, Bradley S. Peters
   Learning as applied to stochastic optimization for standard-cellplacement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:516-527 [Journal]
   
5. Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen
   Timing- and crosstalk-driven area routing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:528-544 [Journal]
   
6. Nur A. Touba, Edward J. McCluskey
   Bit-fixing in pseudorandom sequences for scan BIST. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:545-555 [Journal]
   
7. Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
   Steiner tree optimization for buffers, blockages, and bays. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:556-562 [Journal]