Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2005, volume: 24, number: 7

1. Nahri Moreano, Edson Borin, Cid C. de Souza, Guido Araujo
   Efficient datapath merging for partially reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:969-980 [Journal]
   
2. Zhenhai Zhu, Ben Song, Jacob K. White
   Algorithms in FastImp: a fast and wide-band impedance extraction program for complicated 3-D geometries. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:981-998 [Journal]
   
3. Amit Chowdhary, John P. Hayes
   Area-optimal technology mapping for field-programmable gate arrays based on lookup tables. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:999-1013 [Journal]
   
4. Dongwoo Lee, David Blaauw, Dennis Sylvester
   Static leakage reduction through simultaneous V/sub t//T/sub ox/ and state assignment. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1014-1029 [Journal]
   
5. Le Yan, Jiong Luo, Niraj K. Jha
   Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1030-1041 [Journal]
   
6. Weiping Liao, Lei He, Kevin M. Lepak
   Temperature and supply Voltage aware performance and power modeling at microarchitecture level. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1042-1053 [Journal]
   
7. Shankar Balachandran, Dinesh Bhatia
   A priori wirelength and interconnect estimation based on circuit characteristic. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1054-1065 [Journal]
   
8. Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang
   Spanning graph-based nonrectilinear steiner tree algorithms. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1066-1075 [Journal]
   
9. Kavel M. Büyüksahin, Farid N. Najm
   Early power estimation for VLSI circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1076-1088 [Journal]
   
10. Xun Liu, Marios C. Papaefthymiou
    HyPE: hybrid power estimation for IP-based systems-on-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1089-1103 [Journal]
    
11. Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma
    Layout-aware scan chain synthesis for improved path delay fault coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1104-1114 [Journal]
    
12. Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri
    Fault diagnosis of VLSI circuits with cellular automata based pattern classifier. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1115-1131 [Journal]
    
13. M. Moiz Khan, Spyros Tragoudas
    Rewiring for watermarking digital circuit netlists. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1132-1137 [Journal]
    
14. Fatih Kocan, Mehmet Hadi Gunes
    On the ZBDD-based nonenumerative path delay fault coverage calculation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1137-1143 [Journal]