Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1999, volume: 18, number: 6

1. Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar
   Primitive delay faults: identification, testing, and design for testability. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:669-684 [Journal]
   
2. Ben Mathew, Daniel G. Saab
   Combining multiple DFT schemes with test generation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:685-696 [Journal]
   
3. Mahadevamurty Nemani, Farid N. Najm
   High-level area and power estimation for VLSI circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:697-713 [Journal]
   
4. Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy
   Models and algorithms for bounds on leakage in CMOS circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:714-725 [Journal]
   
5. Catherine H. Gebotys
   A minimum-cost circulation approach to DSP address-code generation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:726-741 [Journal]
   
6. Alain Girault, Bilung Lee, Edward A. Lee
   Hierarchical finite state machines with multiple concurrency models. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:742-760 [Journal]
   
7. Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey
   An output encoding problem and a solution technique. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:761-768 [Journal]
   
8. Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng
   POSET timing and its application to the synthesis and verification of gate-level timed circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:769-786 [Journal]
   
9. Chris C. N. Chu, Martin D. F. Wong
   A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:787-798 [Journal]
   
10. Hirendu Vaishnav, Massoud Pedram
    Delay-optimal clustering targeting low-power VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:799-812 [Journal]
    
11. Luca Benini, Alessandro Bogliolo, Giuseppe A. Paleologo, Giovanni De Micheli
    Policy optimization for dynamic power management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:813-833 [Journal]
    
12. Felice Balarin, Massimiliano Chiodo, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli, Ellen Sentovich, Kei Suzuki
    Synthesis of software programs for embedded control applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:834-849 [Journal]
    
13. Sanghyeon Baeg, William A. Rogers
    A cost-effective design for testability: clock line control and test generation using selective clocking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:850-861 [Journal]
    
14. Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
    Using configurable computing to accelerate Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:861-868 [Journal]