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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1997, volume: 16, number: 10

  1. Joel R. Phillips, Jacob K. White
    A precorrected-FFT method for electrostatic analysis of complicated 3-D structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1059-1072 [Journal]
  2. Qicheng Yu, Carl Sechen
    Efficient approximation of symbolic network functions using matroid intersection algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1073-1081 [Journal]
  3. P. Douglas Yoder, Klaus Gärtner, Ulrich Krumbein, Wolfgang Fichtner
    Optimized terminal current calculation for Monte Carlo device simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1082-1087 [Journal]
  4. Irith Pomeranz, Sudhakar M. Reddy
    On error correction in macro-based circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1088-1100 [Journal]
  5. R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi
    Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1101-1115 [Journal]
  6. N. C. Horta, José E. Franca
    Algorithm-driven synthesis of data conversion architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1116-1135 [Journal]
  7. Enrico Macii, Bernard Plessier, Fabio Somenzi
    Formal verification of digital systems by automatic reduction of data paths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1136-1156 [Journal]
  8. Srimat T. Chakradhar, Anand Raghunathan
    Bottleneck removal algorithm for dynamic compaction in sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1157-1172 [Journal]
  9. Chen-Yang Pan, Kwang-Ting Cheng
    Pseudorandom testing for mixed-signal circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1173-1185 [Journal]
  10. Marcello Dalpasso, Michele Favalli
    A method for increasing the IDDQ testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1186-1188 [Journal]
  11. Wen-Jong Fang, Allen C.-H. Wu
    A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1188-1195 [Journal]
  12. Henrik Floberg, Sven Mattisson
    Symbolic analysis of switched-capacitor networks using compacted nodal analysis in the s-domain. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1196-1199 [Journal]
  13. Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng
    On implementation choices for iterative improvement partitioning algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1199-1205 [Journal]
  14. Noriya Kobayashi, Sharad Malik
    Delay abstraction in combinational logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1205-1212 [Journal]
  15. Chor Ping Low, Hon Wai Leong
    On the reconfiguration of degradable VLSI/WSI arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1213-1221 [Journal]
  16. Wai-Kei Mak, Martin D. F. Wong
    Minimum replication min-cut partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1221-1227 [Journal]
  17. Anand L. Pardhanani, Graham F. Carey
    A mapped Scharfetter-Gummel formulation for the efficient simulation of semiconductor device models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1227-1233 [Journal]
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