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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1999, volume: 18, number: 2

  1. Christoph Scholl, Dirk Möller, Paul Molitor, Rolf Drechsler
    BDD minimization using symmetries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:81-100 [Journal]
  2. Kenneth Y. Yun, David L. Dill
    Automatic synthesis of extended burst-mode circuits. I.(Specification and hazard-free implementations). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:101-117 [Journal]
  3. Kenneth Y. Yun, David L. Dill
    Automatic synthesis of extended burst-mode circuits. II. (Automaticsynthesis). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:118-132 [Journal]
  4. Zhaojun Bai, Rodney D. Slone, William T. Smith, Qiang Ye
    Error bound for reduced system model by Pade approximation via the Lanczos process. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:133-141 [Journal]
  5. Toshiyuki Hama, Hiroaki Etoh
    Topological routing path search algorithm with incremental routability test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:142-150 [Journal]
  6. Witold A. Pleskacz, Charles H. Ouyang, Wojciech Maly
    A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:151-162 [Journal]
  7. Jin-Tai Yan
    An improved optimal algorithm for bubble-sorting-basednon-Manhattan channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:163-171 [Journal]
  8. Edoardo Charbon, Ranjit Gharpurey, Robert G. Meyer, Alberto L. Sangiovanni-Vincentelli
    Substrate optimization based on semi-analytical techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:172-190 [Journal]
  9. Fulvio Corno, Uwe Gläser, Paolo Prinetto, Matteo Sonza Reorda, Heinrich Theodor Vierhaus, Massimo Violante
    SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:191-202 [Journal]
  10. Yuejian Wu, Saman Adham
    Scan-based BIST fault diagnosis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:203-211 [Journal]
  11. Atul Garg, Y. L. Le Coz, Hans J. Greub, R. B. Iverson, Robert F. Philhower, Pete M. Campbell, Cliff A. Maier, Sam A. Steidl, Matthew W. Ernest, Russell P. Kraft, Steven R. Carlough, J. W. Perry, Thomas W. Krawczyk Jr., John F. McDonald
    Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:212-219 [Journal]
  12. Dimitrios Kagaris, Spyros Tragoudas
    On the design of optimal counter-based schemes for test set embedding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:219-230 [Journal]
  13. How-Rern Lin, TingTing Hwang
    On determining sensitization criterion in an iterative gate sizing process. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:231-238 [Journal]
  14. Dhiraj K. Pradhan, Mitrajit Chatterjee
    GLFSR-a new test pattern generator for built-in-self-test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:238-247 [Journal]
  15. Armen H. Zemanian, Victor A. Chang
    Exterior templates for capacitance computations [interconnections]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:248-251 [Journal]
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