Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2001, volume: 20, number: 7

1. C.-J. Richard Shi, Sheldon X.-D. Tan
   Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:7, pp:813-827 [Journal]
   
2. Zaher Baidas, Andrew D. Brown, Alan Christopher Williams
   Floating-point behavioral synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:7, pp:828-839 [Journal]
   
3. Tajana Simunic, Luca Benini, Peter W. Glynn, Giovanni De Micheli
   Event-driven power management. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:7, pp:840-857 [Journal]
   
4. Martin Kuhlmann, Sachin S. Sapatnekar
   Exact and efficient crosstalk estimation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:7, pp:858-866 [Journal]
   
5. Kyu-Il Lee, Jinsoo Kim, Young June Park, Hong Shick Min
   Simple frequency-domain analysis of MOSFET-includingnonquasi-static effect. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:7, pp:867-876 [Journal]
   
6. Phillip Restle, Albert E. Ruehli, Steven G. Walker, George Papadopoulos
   Full-wave PEEC time-domain method for the modeling of on-chipinterconnects. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:7, pp:877-886 [Journal]
   
7. Kenneth L. Shepard, Dae-Jin Kim
   Body-voltage estimation in digital PD-SOI circuits and itsapplication to static timing analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:7, pp:888-901 [Journal]
   
8. Ruiqi Tian, Martin D. F. Wong, Robert Boone
   Model-based dummy feature placement for oxide chemical-mechanicalpolishing manufacturability. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:7, pp:902-910 [Journal]
   
9. Tsung-Chu Huang, Kuen-Jong Lee
   Reduction of power consumption in scan-based circuits during testapplication by an input control technique. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:7, pp:911-917 [Journal]