Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1992, volume: 11, number: 2

1. Bo-Gwan Kim, Donald L. Dietmeyer
   Multilevel logic synthesis with extended arrays. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:142-157 [Journal]
   
2. David W. Knapp, Marianne Winslett
   A prescriptive formal model for data-path hardware. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:158-184 [Journal]
   
3. Kuochen Wang, Sy-Yen Kuo
   Computer-aided modeling and evaluation of reconfigurable VLSI processor arrays with VHDL. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:185-197 [Journal]
   
4. Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel
   PROOFS: a fast, memory-efficient sequential circuit fault simulator. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:198-207 [Journal]
   
5. Mary L. Bailey
   How circuit size affects parallelism. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:208-215 [Journal]
   
6. Uminder Singh, C. Y. Roger Chen
   From logic to symbolic layout for gate matrix. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:216-227 [Journal]
   
7. Takayasu Sakurai, Bill Lin, A. Richard Newton
   Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:228-234 [Journal]
   
8. Yusuf Leblebici, Sung-Mo Kang
   Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:235-246 [Journal]
   
9. Irith Pomeranz, Zvi Kohavi
   A limited exponential complexity algorithm for increasing the testability of digital circuits by testing-module insertion. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:247-259 [Journal]
   
10. Thomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham
    Test compaction for sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:260-267 [Journal]
    
11. Xiaoyu Song
    An algorithm for L-shaped channel routing in a diagonal model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:267-270 [Journal]