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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1992, volume: 11, number: 7

  1. Tom Dhaene, Daniel De Zutter
    Selection of lumped element models for coupled lossy transmission lines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:805-815 [Journal]
  2. Mary L. Bailey
    A time-based model for investigating parallel logic-level simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:816-824 [Journal]
  3. Sharad Malik, Luciano Lavagno, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Symbolic minimization of multilevel logic and the input encoding problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:825-843 [Journal]
  4. Sung-Soo Kim, Chong-Min Kyung
    Circuit placement on arbitrarily shaped regions using the self-organization principle. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:844-854 [Journal]
  5. Stephan Müller, Kevin Kells, Wolfgang Fichtner
    Automatic rectangle-based adaptive mesh generation without obtuse angles. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:855-863 [Journal]
  6. Kenneth M. McDonald, Joseph G. Peters
    Smallest paths in simple rectilinear polygons. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:864-875 [Journal]
  7. Hans-Rudolf Heeb, Wolfgang Fichtner
    A module generator based on the PQ-tree algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:876-884 [Journal]
  8. Scott W. Hadley, Brian L. Mark, Anthony Vannelli
    An efficient eigenvector approach for finding netlist partitions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:885-892 [Journal]
  9. Andrew B. Kahng, Gabriel Robins
    A new class of iterative Steiner tree heuristics with good performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:893-902 [Journal]
  10. Shankar Pennathur, Harry H. L. Kwok
    Simulation of charge transfer in GaAs Cermet-Gate CCDs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:903-910 [Journal]
  11. Edward W. Scheckler, Alexander S. Wong, Robert K. Wang, Goodwin R. Chin, John R. Camagna, Andrew R. Neureuther, Robert W. Dutton
    A utility-based integrated system for process simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:911-920 [Journal]
  12. Hiroyoshi Tanimoto, Naoyuki Shigyo
    Discretization error in MOSFET device simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:921-925 [Journal]
  13. Eun Sei Park, M. Ray Mercer
    An efficient delay test generation system for combinational logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:926-938 [Journal]
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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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