Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1987, volume: 6, number: 1

1. K. C.-K. Weng, Ping Yang, Jue-Hsien Chern
   A Predictor/CAD Model for Buried-Channel MOS Transistors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:4-16 [Journal]
   
2. C. Andrew Neff, Ravi Nair
   A Ranking Algorithm for MOS Circuit Layouts. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:17-21 [Journal]
   
3. Rajiv Kane, Sartaj K. Sahni
   A Systolic Design-Rule Checker. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:22-32 [Journal]
   
4. Dan I. Moldovan
   ADVIS: A Software Package for the Design of Systolic Arrays. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:33-40 [Journal]
   
5. Zhiping Yu, Robert W. Dutton, Massimo Vanzi
   An Extension to Newton's Method in Device Simulators--On An Efficient Algorithm to Evaluate Small-Signal Parameters and to Predict Initial Guess. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:41-45 [Journal]
   
6. Shigeru Takasaki, Tohru Sasaki, Nobuyoshi Nomizu, Nobuhiko Koike, Kenji Ohmori
   Block-Level Hardware Logic Simulation Machine. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:46-54 [Journal]
   
7. Maciej J. Ciesielski, E. Kinnen
   Digraph Relaxation for 2-Dimensional Placement of IC Blocks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:55-66 [Journal]
   
8. K. C. Chang, David Hung-Chang Du
   Efficient Algorithms for Layer Assignment Problem. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:67-78 [Journal]
   
9. Narsingh Deo, Mukkai S. Krishnamoorthy, Michael A. Langston
   Exact and Approximate Solutions for the Gate Matrix Layout Problem. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:79-84 [Journal]
   
10. Silvano Gai, Fabio Somenzi, M. Spalla
    Fast and Coherent Simulation with Zero Delay Elements. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:85-93 [Journal]
    
11. Kenneth J. Supowit
    Finding a Maximum Planar Subset of a Set of Nets in a Channel. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:93-94 [Journal]
    
12. Sangyong Han, Sartaj K. Sahni
    Layering Algorithms For Single-Row Routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:95-102 [Journal]
    
13. Donald E. Thomas, Robert L. Blackburn, Jayanth V. Rajan
    Linking the Behavioral and Structural Domains of Representation for Digital System Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:103-110 [Journal]
    
14. Issac L. Bain, Lance A. Glasser
    Methodology Verification of Hierarchically Described VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:111-115 [Journal]
    
15. K. S. Kumar, J. H. Tracey
    Modeling and Description of Processor-Based Systems with DTMSII. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:116-127 [Journal]
    
16. Vasant B. Rao, Timothy N. Trick
    Network Partitioning and Ordering for MOS VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:128-144 [Journal]
    
17. K. Komatsu, M. Suzuki
    The Outline Procedure in Pattern Data Preparation for Vector-Scan Electron-Beam Lithography. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:145-151 [Journal]