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Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1988, volume: 7, number: 4

  1. J.-N. Song, Y.-K. Chen
    Two-stage channel routing for CMOS gate arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:4, pp:439-450 [Journal]
  2. Wayne Wolf, Robert G. Mathews, John A. Newkirk, Robert W. Dutton
    Algorithms for optimizing, two-dimensional symbolic layout compaction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:4, pp:451-466 [Journal]
  3. Sartaj K. Sahni, San-Yuan Wu
    Two NP-hard interchangeable terminal problems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:4, pp:467-472 [Journal]
  4. Surendra Nahar, Sartaj K. Sahni
    Fast algorithm for polygon decomposition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:4, pp:473-483 [Journal]
  5. Allan Silburt, A. R. Boothroyd, M. Digiovanni
    Automated parameter extraction and modeling of the MOSFET below threshold. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:4, pp:484-488 [Journal]
  6. Christian H. Corbex, Anne F. Gerodelle, Serge P. Martin, Alain R. Poncet
    Data structuring for process and device simulations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:4, pp:489-500 [Journal]
  7. William Nye, David C. Riley, Alberto L. Sangiovanni-Vincentelli, André L. Tits
    DELIGHT.SPICE: an optimization-based system for the design of integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:4, pp:501-519 [Journal]
  8. Bing J. Sheu, Wen-Jay Hsu, P. K. Ko
    An MOS transistor charge model for VLSI design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:4, pp:520-527 [Journal]
  9. Chin-Long Wey
    On yield consideration for the design of redundant programmable logic arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:4, pp:528-535 [Journal]
  10. M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders, Jayanti C. Majithia
    Allocation of multiport memories in data path synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:4, pp:536-540 [Journal]
  11. Jerry G. Fossum, Surya Veeraraghavan, Dan Fitzpatrick
    Model selection for SOI MOSFET circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:4, pp:541-544 [Journal]
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