Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2000, volume: 19, number: 7

1. Florin Balasa, Koen Lampaert
   Symmetry within the sequence-pair representation in the context ofplacement for analog design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:721-731 [Journal]
   
2. Jui-Ming Chang, Massoud Pedram
   Codex-dp: co-design of communicating systems using dynamicprogramming. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:732-744 [Journal]
   
3. Zhao-Xuan Shen, Ching Chuen Jong
   Functional area lower bound and upper bound on multicomponentselection for interval scheduling. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:745-759 [Journal]
   
4. Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto
   Symbolic optimization of interacting controllers based onredundancy identification and removal. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:760-772 [Journal]
   
5. Dingming Xie, Leonard Forbes
   Phase noise on a 2-GHz CMOS LC oscillator. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:773-778 [Journal]
   
6. Kishore Kasamsetty, Mahesh Ketkar, Sachin S. Sapatnekar
   A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:779-788 [Journal]
   
7. Bapiraju Vinnakota, Ramesh Harjani
   DFT for digital detection of analog parametric faults in SC filters. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:789-798 [Journal]
   
8. Pavan K. Gunupudi, Michel S. Nakhla, Ramachandra Achar
   Simulation of high-speed distributed interconnects usingKrylov-space techniques. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:799-808 [Journal]
   
9. Subodh Gupta, Farid N. Najm
   Analytical models for RTL power estimation of combinational andsequential circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:808-814 [Journal]
   
10. C. A. J. van Eijk
    Sequential equivalence checking based on structural similarities. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:814-819 [Journal]
    
11. Hai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz
    Simultaneous routing and buffer insertion with restrictions onbuffer locations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:819-824 [Journal]