Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1989, volume: 8, number: 9

1. Bharat L. Bhuva, John J. Paulos, Ronald S. Gyurcsik, Sherra E. Kerns
   Switch-level simulation of total dose effects on CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:933-938 [Journal]
   
2. Michael D. Deal, S. E. Hansen, Thomas W. Sigmon
   SUPREM 3.5-process modeling of GaAs integrated circuit technology. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:939-951 [Journal]
   
3. Fabrizio Lombardi, Mariagiovanna Sami, Renato Stefanelli
   Reconfiguration of VLSI arrays by covering. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:952-965 [Journal]
   
4. Yuzo Takamatsu, Kozo Kinoshita
   CONT: a concurrent test generation system. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:966-972 [Journal]
   
5. Sreejit Chakravarty
   On the complexity of computing tests for CMOS gates. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:973-980 [Journal]
   
6. Hong Cai, Ralph H. J. M. Otten
   Conflict-free channel definition in building-block layout. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:981-988 [Journal]
   
7. I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man
   REDUSA: module generation by automatic elimination of superfluous blocks in regular structures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:989-998 [Journal]
   
8. Xianjin Yao, Masaaki Yamada, C. L. Liu
   A new approach to the pin assignment problem. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:999-1006 [Journal]
   
9. B. Gurunath, Nripendra N. Biswas
   An algorithm for multiple output minimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:1007-1013 [Journal]
   
10. J. E. (Ned) Lecky, O. J. Murphy, Richard Absher
    Graph theoretic algorithms for the PLA folding problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:1014-1021 [Journal]
    
11. Hideo Fujiwara
    Enhancing random-pattern coverage of programmable logic arrays via masking technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:1022-1025 [Journal]
    
12. Çetin Kaya Koç, P. F. Ordung
    Schwarz-Christoffel transformation for the simulation of two-dimensional capacitance [VLSI circuits]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:1025-1027 [Journal]
    
13. Young-Hyun Jun, Ki Jun, Song-Bai Park
    An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:1027-1032 [Journal]