Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2004, volume: 23, number: 2

1. Florin Balasa, Sarat C. Maruvada, Karthik Krishnamoorthy
   On the exploration of the solution space in analog placement with symmetry constraints. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:177-191 [Journal]
   
2. Giorgio Biagetti, Simone Orcioni, Claudio Turchetti, Paolo Crippa, Michele Alessandrini
   SiSMA-a tool for efficient analysis of analog CMOS integrated circuits affected by device mismatch. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:192-207 [Journal]
   
3. Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong
   Effective iterative techniques for fingerprinting design IP. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:208-215 [Journal]
   
4. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
   Custom-instruction synthesis for extensible-processor platforms. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:216-228 [Journal]
   
5. Geun Rae Cho, Tom Chen
   Synthesis of single/dual-rail mixed PTL/static logic for low-power applications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:229-242 [Journal]
   
6. Mahmut T. Kandemir, J. Ramanujam, Mary Jane Irwin, Narayanan Vijaykrishnan, Ismail Kadayif, Amisha Parikh
   A compiler-based approach for dynamically managing scratch-pad memories in embedded systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:243-260 [Journal]
   
7. Mehdi Baradaran Tahoori, Subhasish Mitra
   Techniques and algorithms for fault grading of FPGA interconnect test configurations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:261-272 [Journal]
   
8. B. K. S. V. L. Varaprasad, Lalit M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal
   A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:273-287 [Journal]
   
9. Michael W. Beattie, Lawrence T. Pileggi
   Parasitics extraction with multipole refinement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:288-292 [Journal]
   
10. Carlos P. Coelho, Joel R. Phillips, Luis Miguel Silveira
    A convex programming approach for generating guaranteed passive approximations to tabulated frequency-data. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:293-301 [Journal]
    
11. Sumit Gupta, Nicolae Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau
    Using global code motions to improve the quality of results for high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:302-312 [Journal]
    
12. Sandip Kundu
    Pitfalls of hierarchical fault simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:312-314 [Journal]
    
13. Wai-Kei Mak
    I/O placement for FPGAs with multiple I/O standards. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:315-321 [Journal]
    
14. Kohei Miyase, Seiji Kajihara
    XID: Don't care identification of test patterns for combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:321-326 [Journal]