Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1988, volume: 7, number: 8

1. Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman
   SLS-a fast switch-level simulator [for MOS]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:8, pp:838-849 [Journal]
   
2. K. Garwacki
   Extraction of BJT model parameters using optimization method. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:8, pp:850-854 [Journal]
   
3. Jan J. H. van der Biesen, Toru Toyabe
   Comparison of methods to calculate capacitances and cutoff frequencies from DC and AC simulations on bipolar devices. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:8, pp:855-861 [Journal]
   
4. J. Gregory Rollins, John Choma Jr.
   Mixed-mode PISCES-SPICE coupled circuit and device solver. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:8, pp:862-867 [Journal]
   
5. Youn-Long Lin, Daniel D. Gajski
   LES: a layout expert system. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:8, pp:868-876 [Journal]
   
6. Richard I. Hartley, Jeffrey R. Jasica
   Behavioral to structural translation in a bit-serial silicon compiler. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:8, pp:877-886 [Journal]
   
7. Chidchanok Lursinsap, Daniel D. Gajski
   A technique for pull-up transistor folding. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:8, pp:887-896 [Journal]
   
8. Peter M. Maurer, Alexander D. Schapira
   A logic-to-logic comparator for VLSI layout verification. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:8, pp:897-907 [Journal]
   
9. Edmund M. Clarke, Yulin Feng
   Escher-a geometrical layout system for recursively defined circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:8, pp:908-918 [Journal]
   
10. Kwanghyun Kim, Dong Sam Ha, Joseph G. Tront
    On using signature registers as pseudorandom pattern generators in built-in self-testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:8, pp:919-928 [Journal]
    
11. Rex E. Lowther
    The solution of a numerical problem encountered when adding a mobility model to a finite-element device simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:8, pp:929-930 [Journal]