The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2006, volume: 25, number: 10

  1. Lihong Zhang, Rabin Raut, Yingtao Jiang, Ulrich Kleine
    Placement Algorithm in Analog-Layout Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:1889-1903 [Journal]
  2. Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Christos P. Sotiriou
    Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:1904-1921 [Journal]
  3. Prasenjit Basu, Sayantan Das, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni
    Design-Intent Coverage - A New Paradigm for Formal Property Verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:1922-1934 [Journal]
  4. J.-G. Lee, C.-M. Kyung
    PrePack: Predictive Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:1935-1949 [Journal]
  5. Sebastien Bilavarn, Guy Gogniat, Jean Luc Philippe, Lilian Bossuet
    Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:1950-1968 [Journal]
  6. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Use of Computation-Unit Integrated Memories in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:1969-1989 [Journal]
  7. Dong-U Lee, Altaf Abdul Gaffar, Ray C. C. Cheung, Oskar Mencer, Wayne Luk, George A. Constantinides
    Accuracy-Guaranteed Bit-Width Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:1990-2000 [Journal]
  8. Sarma B. K. Vrudhula, Janet Meiling Wang, Praveen Ghanta
    Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2001-2011 [Journal]
  9. Anup Hosangadi, Farzan Fallah, Ryan Kastner
    Optimizing Polynomial Expressions by Algebraic Factorization and Common Subexpression Elimination. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2012-2022 [Journal]
  10. Yan Lin, Lei He
    Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2023-2034 [Journal]
  11. Manish Verma, Lars Wehmeyer, Peter Marwedel
    Cache-Aware Scratchpad-Allocation Algorithms for Energy-Constrained Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2035-2051 [Journal]
  12. S. Mukhopadhyay, K. Kim, C. T. Chuang, K. Roy
    Modeling and Analysis of Leakage Currents in Double-Gate Technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2052-2061 [Journal]
  13. N. Wong, V. Balakrishnan, C.-K. Koh, T.-S. Ng
    Two Algorithms for Fast and Accurate Passivity-Preserving Model Order Reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2062-2075 [Journal]
  14. Andrew A. Kennings, Kristofer Vorwerk
    Force-Directed Methods for Generic Placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2076-2087 [Journal]
  15. Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh
    Statistical Analysis and Design of HARP FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2088-2102 [Journal]
  16. Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    RTL-Aware Cycle-Accurate Functional Power Estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2103-2117 [Journal]
  17. J. Cervenka, W. Wessner, E. Al-Ani, Tibor Grasser, Siegfried Selberherr
    Generation of Unstructured Meshes for Process and Device Simulation by Means of Partial Differential Equations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2118-2128 [Journal]
  18. W. Wessner, J. Cervenka, Clemens Heitzinger, Andreas Hössinger, Siegfried Selberherr
    Anisotropic Mesh Refinement for the Simulation of Three-Dimensional Semiconductor Manufacturing Processes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2129-2139 [Journal]
  19. Ming Zhang, Naresh R. Shanbhag
    Soft-Error-Rate-Analysis (SERA) Methodology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2140-2155 [Journal]
  20. Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
    Voltage-Aware Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2156-2169 [Journal]
  21. Chandramouli Visweswariah, K. Ravindran, K. Kalafala, Steven G. Walker, S. Narayan, Daniel K. Beece, J. Piaget, N. Venkateswaran, Jeffrey G. Hemmett
    First-Order Incremental Block-Based Statistical Timing Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2170-2180 [Journal]
  22. Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
    Simulating Resistive-Bridging and Stuck-At Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2181-2192 [Journal]
  23. Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar
    Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2193-2206 [Journal]
  24. Irith Pomeranz, Sudhakar M. Reddy
    Generation of Functional Broadside Tests for Transition Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2207-2218 [Journal]
  25. Irith Pomeranz, Sudhakar M. Reddy
    Using Dummy Bridging Faults to Define Reduced Sets of Target Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2219-2227 [Journal]
  26. Marc-André Cantin, Yvon Savaria, D. Prodanos, Pierre Lavoie
    A Metric for Automatic Word-Length Determination of Hardware Datapaths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2228-2231 [Journal]
  27. M. Capobianchi, V. Labay, F. Shi, G. Mizushima
    Simulating the Electrical Behavior of Integrated Circuit Devices in the Presence of Thermal Interactions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2231-2241 [Journal]
  28. Valentina Ciriani, Anna Bernasconi, Rolf Drechsler
    Testability of SPP Three-Level Logic Networks in Static Fault Models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2241-2248 [Journal]
  29. Jacob R. Minz, Sung Kyu Lim
    Block-level 3-D Global Routing With an Application to 3-D Packaging. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2248-2257 [Journal]
  30. S.-W. Tu, Y.-W. Chang, J.-Y. Jou
    RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2258-2264 [Journal]
  31. Janet Meiling Wang, Jun Li, Satish K. Yanamanamanda, Lakshmi Kalpana Vakati, Kishore Kumar Muchherla
    Modeling the Driver Load in the Presence of Process Variations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2264-2275 [Journal]
  32. Qingwei Wu, Michael S. Hsiao
    State Variable Extraction and Partitioning to Reduce Problem Complexity for ATPG and Design Validation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2275-2282 [Journal]
  33. Shu Yan, Vivek Sarin, Weiping Shi
    Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2282-2286 [Journal]
  34. Bo Yang, Kaijie Wu, Ramesh Karri
    Secure Scan: A Design-for-Test Architecture for Crypto Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2287-2293 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002