The SCEAS System
Navigation Menu

Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1996, volume: 15, number: 5

  1. Ping-Chung Li, Ibrahim N. Hajj
    Computer-aided redesign of VLSI circuits for hot-carrier reliability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:453-464 [Journal]
  2. Tong Gao, C. L. Liu
    Minimum crosstalk channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:465-474 [Journal]
  3. William R. Bandy, Raymond S. Winton
    A new approach for modeling the MOSFET using a simple, continuous analytical expression for drain conductance which includes velocity-saturation in a fundamental way. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:475-483 [Journal]
  4. Slobodan Mijalkovic
    Exponentially fitted discretization schemes for diffusion process simulation on coarse grids. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:484-492 [Journal]
  5. Alper Demir, Edward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli
    Time-domain non-Monte Carlo noise simulation for nonlinear dynamic circuits with arbitrary excitations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:493-505 [Journal]
  6. Timo Koskinen, Peter Y. K. Cheung
    Hierarchical tolerance analysis using statistical behavioral models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:506-516 [Journal]
  7. Joseph M. Wolf, Lori M. Kaufman, Robert H. Klenke, James H. Aylor, Ronald Waxman
    An analysis of fault partitioned parallel test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:517-534 [Journal]
  8. Jin-fuw Lee, Donald T. Tang, Chak-Kuen Wong
    A timing analysis algorithm for circuits with level-sensitive latches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:535-543 [Journal]
  9. Florentin Dartu, Noel Menezes, Lawrence T. Pileggi
    Performance computation for precharacterized CMOS gates with RC loads. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:544-553 [Journal]
  10. Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien
    Spectral-based multiway FPGA partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:554-560 [Journal]
  11. Chunghee Kim, Hyunchul Shin
    A performance-driven logic emulation system: FPGA network design and performance-driven partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:560-568 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002